Iffat Jahan
CV

Digital logic · In the CV

6-Bit Computer (Modified SAP-1)

Designed a 6-bit computer with fewer T-states and a 3-digit display showing carry and sign.

  • Proteus (simulation and PCB layout)
  • 74-series logic ICs

About

A 6-bit computer whose display uses three 7-segment digits instead of four, reducing hardware. A custom memory circuit shows the carry bit and the negative sign, and an optimised controller-sequencer reduces the number of T-states, improving speed and efficiency.

Published as [C1]: S. Saif, I. Jahan, A. M. Maisha and M. M. Billah, “6-Bit Computer Implementation with Optimized Display and Reduced T-states,” IUT-ICCET 2024, Dept. of EEE, IUT, Gazipur, Bangladesh, 2024. All publications

How to run

  • Open the project in Proteus 8 Professional, version 8.17 or newer. The PCB archive holds the board layouts of the individual units.